This application generally relates to the field of phase locked oscillators.
A phase-locked loop (PLL) circuit is an electronic control circuit that generates an output clock signal having a phase that is locked to the phase of an input reference signal. By using a highly stable input reference signal, the output clock signal can be made to be also highly stable. A PLL circuit is commonly used in communication devices, computers, and other electronic devices. An analog PLL circuit uses analog components to provide the phase-lock architecture. These analog components include a phase detector, a voltage-controlled oscillator (VCO), and a feedback path between the VCO output signal and an input port of the phase detector. By connecting the input reference signal to another input port of the phase detector, the output of the phase detector may be used to adjust the phase of the VCO output signal until that phase is locked to the input reference signal.
A PLL circuit may also be implemented using all digital components. Such a PLL circuit is known as an all-digital PLL (ADPLL) circuit. Like its analog counterpart, an ADPLL circuit uses a feedback path to return a digitally-controlled oscillator (DCO) clock signal to generate a digital phase error signal based on the output from a time-to-digital converter (TDC) and a reference phase signal. In response to the digital phase error signal, the phase of the DCO clock signal is adjusted.
Embodiments of the present invention will be described with reference to the accompanying drawings.